Japanese Unexamined Patent Publication No. Hei 11(1999)-329000 describes a semiconductor integrated circuit having a BIST circuit capable of high-speed processing by command sequencers and internal clock generating circuits. This sequencer-based BIST technology is limited by the available number and type of test sequences, and hence does not cover a variety of test sequences.
Japanese Unexamined Patent Publication No. Hei 11(1998)-162600 describes semiconductor storage with a built-in BIST circuit comprising a test clock generator, an address counter, and a sequencer. The circuit scale of this built-in BIST circuit increases when a PLL circuit is adopted as the test clock generator. This is because the PLL circuit requires a voltage controlled oscillator and a D/A converter, and thus requires a voltage controlled current source and additional circuitry.
Further, if data retention tests for semiconductor storages, such as DRAM, are used, the wait time for the data retention test may eliminate the usefulness of a high-speed tester. However, in the known art the use of a low-speed tester has also been highly undesirable.
Thus, the need exists for a semiconductor device and method having a BIST circuit that provides an acceptable testing time without necessitating a substantial increase in circuit area.